1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit memories, and more particularly to a semiconductor integrated circuit memory which operates in synchronism with a clock.
Recently, semiconductor memory devices such as DRAM (Dynamic Random Access Memory) devices have been required to input and output data at higher frequencies in accordance with speeding up of CPUs so that the data transmission rate can be increased.
An SDRAM (Synchronous DRAM) device and FCRAM (Fast Cycle RAM) can operate at a high speed in synchronism with a clock signal supplied from the outside of the device.
2. Description of the Related Art
FIG. 1 illustrates a circuit configuration of a periphery of a memory cell of the SDRAM. The circuit shown in FIG. 1 includes a capacitor 201, NMOS (N-channel Metal Oxide Semiconductor) transistors 212, 223 and 224, and PMOS (P-channel MOS) transistors 213, 221 and 222. The PMOS transistors 221 and 222 and the NMOS transistors 223 and 224 form a sense amplifier 220.
The capacitor 201, which forms a memory cell, can store one-bit data. The data stored in the capacitor 201 is read onto a pair of data bus lines DB and /DB as follows.
FIG. 2 is a timing chart of a read operation of the SDRAM having the memory cell peripheral circuit shown in FIG. 1. A description will now be given of a timing control of the data read operation with reference to FIGS. 1 and 2.
At the time of reading data, commands are sequentially applied to the SDRAM. More particularly, the SDRAM is supplied with a precharge command (PRE), a row address strobe signal /RAS (R), and a column address strobe signal /CAS (C). The precharge command is used to precharge a pair of bit lines BL and /BL to a predetermined potential. The row address strobe signal /RAS is used to select a memory cell block of the row system from a core circuit of the SDRAM, that is, to select a word line. The column address strobe signal /CAS is used to select a column, that is, the sense amplifier 220. The core circuit includes a plurality of memory cells 201 that are arrayed in the row and column directions. Each column is provided with the respective sense amplifier 220. Hence, the selected sense amplifier 220 senses data from the memory cell connected to the selected word line.
When the row address strobe signal /RAS is input to the SDRAM, a bit line transfer signal BLT0 is switched to the low level. At that time, a bit line transfer signal BLT1 is at the high level, and the NMOS transistors 203 and 204 are in the conducting states. Hence, the bit lines BL and /BL are connected to the sense amplifier 220. Simultaneously, a precharge signal PR is switched to the low level, and thus the bit lines BL and /BL are released from the reset state.
Then, a sub word line select signal SW is selected so that it is switched to the high level. Hence, the corresponding word line is selected, and the NMOS transistor 202 is caused to conduct. Hence, data stored in the capacitor 201 is read to the bit line BL.
Then, sense amplifier drive signals SA1 and SA2 are activated in order to drive the sense amplifier 220. Thus, the NMOS transistor 212 and the PMOS transistor 213 are turned ON. In that state, the data on the bit lines BL and /BL are read by the sense amplifier 220 via the NMOS transistors 203 and 204. Then, the sense amplifier 220 amplifies the data on the bit lines BL and /BL, and the amplitude between the bit lines BL and /BL is increased. At that time, data stored in the memory cells connected to the selected word line are read and amplified by the respective sense amplifiers 220.
Thereafter, a column line select signal CL switches to the high level in response to the column address strobe signal /CAS, and the corresponding column is selected. Then, the NMOS transistors 210 and 211 of the selected column gate are turned ON, and the amplified data on the bit lines BL and /BL are read to the data bus lines DB and /DB.
In order to successively read data related to the same row address (the same word line) in the single-bank configuration, different columns are sequentially selected by sequentially setting the column line select signals to the high level. Hence, the data already stored in the sense amplifiers and specified by the different column address values are sequentially read. When the burst length L is equal to 4, 4 consecutive bits of data can be read as shown in FIG. 2.
Thereafter, the precharge command is input. Hence, the precharge signal PR is switched to the high level at an appropriate timing. Hence, the NMOS transistors 207, 208 and 209 are turned ON, and the bit lines BL and /BL are set to a given potential VPR. Hence, the bit lines BL and /BL are reset, and are ready to the next control signal (R or W).
However, when the commands (R), (C) and (PRE) are input again in order to read data from a different row address (different word line), it is required to newly read data from the memory cells newly selected by the above commands and output the read data to the bit lines BL and /BL. In the single-bank configuration, it is required to precharge the bit lines BL and /BL in order to newly output data to the bit lines BL and /BL. Hence, a long blank period equal to 10 clocks occurs until the next data are read, as shown in FIG. 2.
In order to fill up the blank period, a bank interleaving method is employed in the SDRAM of the multi-bank configuration. In the bank interleaving method, command are applied so that a plurality of banks are sequentially selected and data are sequentially output from each selected bank at the respective timings. As shown in the lower part of FIG. 2, the commands are sequentially applied to banks 0 and 1. Hence, read data from the bank 1 can be output during the 10-clock blank period related to the bank 0.
There is an FCRAM, which is one of the semiconductor memories. A description will be given of the difference between the SDRAM and the FCRAM and a data read timing control of the FCRAM. The configuration of the peripheral circuits of the memory cells of the FCRAM is the same as that of the SDRAM.
In the first difference, the FCRAM is configured so that a plurality of columns are read at one time and data are read from the sense amplifiers 220 in parallel. Hence, it is sufficient to drive the sense amplifiers 220 during a fixed period. That is, the operation period of the sense amplifiers 220 can be set to a constant length regardless of the burst length BL. For instance, the operation periods of the amplifiers 220 with BL equal to 1 are the same as those with BL equal to 4. Hence, a reliable pipeline operation of the row system can be realized.
In the second difference, the FCRAM employs an internal precharge signal (which corresponds to the precharge signal (PRE) employed in the SDRAM). The internal precharge signal is used to automatically perform the reset operation. The automatic reset operation utilizes the fact that the sense amplifiers operate during only the constant period. The precharge operation is carried out at an appropriate timing immediately after data are read from the sense amplifiers 220. Hence, it is possible to realize the data read operation in fast cycles close to the critical driving capability of the sense amplifiers 220.
In the third difference, the FCRAM has the read cycle in random access shorter than that of the SDRAM. This is because the FCRAM employs the pipeline operation and the self-precharge operation. For example, when the burst length BL is equal to 4 as in the case of the SDRAM, the 4-bit parallel data read from the sense amplifiers are converted into serial data. Hence, data can serially be read without any interruption.
FIG. 3 is a timing chart of the data read operation of the FCRAM having the memory peripheral circuits shown in FIG. 1. The data read timing control of the FCRAM will be described with reference to FIGS. 1 and 3. The burst length BL of read data is equal to 4 as in the case of the SDRAM shown in FIG. 2.
In response to an activation command (ACT), a signal RASZ is generated in the FCRAM. The signal RASZ instructs data of the memory cells 201 to be latched in the sense amplifiers 220. Further, in the FCRAM, generated are main and sub word line select signals MW and SW, the bit line transfer signal BLT, and the sense amplifier drive signals SA1 and SA2 at respective appropriate timings. Hence, data stored in the memory cells 201 appear on the bit lines BL, and are latched and amplified in the sense amplifiers 220.
Further, the internal precharge signal PRE is generated in the FCRAM when a given time elapses after the signal RASZ is received.
Furthermore, in response to the read command (RD), the column line select signals CL related to the column selected by the column address are switched to the high level, and data stored in the sense amplifier 220 are read out to the data bus lines DB and /DB. The data thus read are 4-bit parallel data, which are converted into serial data. Finally, the serial data is output to the outside of the FCRAM as read data DQ.
As shown in FIG. 3, the internal precharge signal PRE generated in the FCRAM resets the bit line transfer signal BLT and the word line select signals MW and SW, and precharges the bit lines BL and /BL to the given potential. The timing of the precharge operation responsive to the internal precharge signal PRE is placed immediately after the data are read from the sense amplifiers 220 in response to the column line select signals CL.
In the FCRAM, commands are received in a packet formation in order to reduce the intervals between the commands. As shown in FIG. 3, the activation command (ACT) and the read command (RD) are input as a single packet which extends over two cycles.
When the data read operation is repeatedly carried out, data can serially be read without any interruption with the burst length BL equal to four because the read cycle of the random access is comparatively short. That is, the FCRAM does not need the bank interleaving method employed in the SDRAM.
As described above, the FCRAM does not have the blank period which occurs in the SDRAM at the time of reading data, and can read data at a higher speed.
Theoretically, as the number of bits of data to be simultaneously read in parallel increases, the burst length increases. This requires that the potential differences between an increased number of pairs of bit lines connected to the selected word line are simultaneously amplified and the pairs of bit lines are simultaneously reset. This causes a delay in the read operation.
It is preferable that the core size be as small as possible in order to speed up the read operation. This, however, leads to a reduction in the number bits which can be simultaneously read in parallel. Nowadays, there is a requirement that a large number of bits of data can be simultaneously read at a higher speed. Such a tradeoff requirement cannot be satisfied at the present time.